7th
09,05
For EE Major, there is last, but most notorious class, called Lab3 (officially Design Lab). There is Lab1, Lab2 and lastly Lab3 (Lab4 is option – I did). Among all of Lab classes, Lab3 is the most demanding. Since it is so tough, we have to spend 3~5 days in a lab including 2 official days. At least 2 night standings are normal for layman.
I and my lab mate completed to implement a complete Digital Storage Oscilloscope. As you can see the picture, our digital oscilloscope display 2 channel signal-200 kHz at maximum. It includes trigger level control, x1000 programmable gain amplifier and frequency analysis. In this picture, a blue signal comes from microphone, separate circuit from bread board.
Frankly, the most difficult part is to design FPGA with Verilog. Since it has to generate 20MHz sampling signal to capture signal in 8bits ADC and to write them into a FIFO. In addition, reducing noisy by separating analog and digital circuit is also hard. On top of that, managing a gain and frequency of signals passing through a couple of Op-Amps is not easy job.
However, we completed all circuits in one interface board on the provided embedded board. Wow!